The visibility of component power behavior is provided through the use of IP power models, which are created for power estimation at higher levels of design. An IP power model is an abstraction of the power behavior of a component that provides specification of the supported component power state and power consumption data. The IP power model may provide power consumption data for each enumerated power state (e.g., functional mode, test mode, etc.) in the power model which may significantly impact the overall power consumption of the component. Determining the simulation condition for the different input pins of the IP blocks is critical to generate an accurate power model. Poorly constructed power models may cause erroneous power analysis and subsequent chip or system power projections. Similarly, there may be instances in a design where the IP block input pin conditions have been violated. However, due to the rapid growth and complexity of systems, such as microprocessors, generation of IP power models and verification of IP designs have become increasingly difficult, are time consuming, and are prone to error.